1. Field of the Invention
The present invention generally relates to SAR ADCs.
2. Related Art
In current successive approximation register analog-to-digital converter (SAR ADC) implementations, most of digital-to-analog converters (DACs) are implemented capacitively. The problem with capacitive DACs is that they are large in size, and due to their nature of implementation they tend to limit bandwidth, which can translate into high current consumption for high speed. Current mode DACS can also be used, but are limited by noise of the active current sources, and have relatively high current consumption.
Also, due to the nature of the successive approximation search algorithm, traditional SAR ADCs typically use N+1 or N+2 cycles to complete a single conversion from an analog signal to a digital signal. Where N corresponds to the ADC resolution, e.g., 8 bits, the SAR ADC typically would require 8+1=9 cycles to complete 1 cycle of conversion.
Therefore, what is needed is a SAR ADC that alleviates the problems with using capacitive and current mode DACs, and possibly reduces a required number of cycles for conversion.